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EN29LV641H/L EN29LV640U EN29LV641H/L EN29LV640U 64 Megabit (4096K x 16-bit) Flash Memory, CMOS 3.0 Volt-only Uniform Sector Flash Memory
FEATURES
* Single power supply operation - Full voltage range: 2.7 to 3.6 volts for read, erase and program operations * Low power consumption (typical values at 5 MHz) - 9 mA typical active read current - 20 mA typical program/erase current
- Less than 1 A current in standby or automatic sleep mode.
Software features: * Sector Group Protection - Provide locking of sectors to prevent program or erase operations within individual sectors - Additionally, temporary Sector Group Unprotect allows code changes in previously protected sectors. * Standard DATA# polling and toggle bits feature * Unlock Bypass Program command supported * Sector Erase Suspend / Resume modes: Read and program another Sector during Sector Erase Suspend Mode * Support JEDEC Common Flash Interface (CFI). Hardware features: * RESET# hardware reset pin - Hardware method to reset the device to read mode. * WP# input pin - Write Protect (WP#) function allows protection of first or last 32K-word sector, regardless of previous sector protect status * ACC input pin - Acceleration (ACC) function provides accelerated program times for higher throughput for manufacturing.
* JEDEC standards compatible - Pinout and software compatible with singlepower supply Flash standard * Manufactured on 0.18 m process technology * Flexible Sector Architecture: - One hundred and twenty-eight 32K-Word sectors. * Minimum 100K program/erase endurance cycles. * High performance for program and erase Word program time: 8s typical Sector Erase time: 500ms typical Chip Erase time: 64s typical
* Package Options - 48-pin TSOP - 63 ball 11mm x 12mm FBGA
GENERAL DESCRIPTION
The EN29LV641H/L / EN29LV640U is a 64-Megabit (4,194,304x16), electrically erasable, read/write non-volatile flash memory. Any word can be programmed typically in 8s. This device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The EN29LV641H/L / EN29LV640U is designed to allow either single Sector or full Chip erase operation, where each Sector Group can be protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications.
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
PRODUCT SELECTOR GUIDE
Product Number Regulated Voltage Range: VCC=3.0 - 3.6 V Speed Option Full Voltage Range: VCC=2.7 - 3.6 V Max Access Time (ns) Max CE# Access Time (ns) Max OE# Access Time (ns) 70 70 30 90 90 90 35 EN29LV641H/L / EN29LV640U 70R
BLOCK DIAGRAM
VCC VSS RESET# State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
RY/BY#
Sector Protect Switches
DQ15-DQ0
Erase Voltage Generator Input/Output Buffers
WE# WP# ACC#
Command Register CE# OE#
Data Latch
Y-Decoder Address Latch
STB
Y-Gating
VCC Detector
Timer
X-Decoder
Cell Matrix
A21-A0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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CONNECTION DIAGRAMS
Note: No RY/BY# pin for TSOP package , VIO should be tied directly to VCC.
Note: No WP# pin for FBGA package VIO should be tied directly to VCC.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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TABLE 1. PIN DESCRIPTION LOGIC DIAGRAM
Pin Name A21-A0 DQ15-DQ0 CE# OE# WE# WP# ACC RY/BY# RESET# Vcc VIO Vss NC
Function 22 Address inputs 16 Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Hardware Write Protect Input Acceleration Input Ready/Busy status output Hardware Reset Input Pin Supply Voltage (2.7-3.6V) Output Buffer Power Supply this pin should be tied directly to VCC Ground Not Connected to anything Note: WP# pins are for EN29LV641H/L only. RY/BY# is available for EN29LV640U only.
A21 - A0 CE# OE# WE# WP# ACC RESET# VIO RY/BY# DQ15 - DQ0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
ORDERING INFORMATION
EN29LV641 H 90 T I P PACKAGING CONTENT (Blank) = Conventional P = Pb Free TEMPERATURE RANGE I = Industrial (-40C to +85C) C = Commercial (0C to +70C) PACKAGE T = 48-pin TSOP W= 63-Ball Fine Pitch Ball Grid Array (FBGA) 0.80mm pitch, 11mm x 12mm package SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR for WRITE PROTECT (WP#=0) H = highest address sector protected L = lowest address sector protected BASE PART NUMBER EN29LV641 / EN29LV640U 64 Megabit(4M x 16-Bit) Uniform Sector Flash Optional Data I/O voltage 3V Read, Erase and Program
PRODUCT SELECTOR GUIDE
Valid Combinations for TSOP Packages EN29LV641H 90 EN29LV641L 90 EN29LV641H 70R, EN29LV641L 70R Vcc Vcc = 2.7V-3.6V TI, TC Vcc = 3.0V-3.6V
Valid Combinations for FBGA Packages EN29LV640U EN29LV640U 90 70R WI, WC
Vcc Vcc = 2.7V-3.6V Vcc = 3.0V-3.6V
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Table 2. Sector (Group) Address Tables
Sector Group Protect/Unprotect Sector Group A21-A17 Sector
SA0 SA1 SG0 00000 SA2 SA3 SA4 SA5 SG1 00001 SA6 SA7 SA8 SA9 SG2 00010 SA10 SA11 SA12 SA13 SG3 00011 SA14 SA15 SA16 SA17 SG4 00100 SA18 SA19 SA20 SA21 SG5 00101 SA22 SA23 SA24 SA25 SG6 00110 SA26 SA27 SA28 SA29 SG7 00111 SA30 SA31 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0F0000-0F7FFF 0F8000-0FFFFF 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF
Sector Address Range for Sector Erase A21
0 0
A20
0 0
A19
0 0
A18
0 0
A17
0 0
A16
0 0
A15
0 1
Address Range (hexadecimal)
000000-007FFF 008000-00FFFF
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Sector Group
A21-A17
Sector
SA32 SA33
A21
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A20
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (hexadecimal)
100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF
SG8
01000 SA34 SA35 SA36 SA37
SG9
01001 SA38 SA39 SA40 SA41
SG10
01010 SA42 SA43 SA44 SA45
SG11
01011 SA46 SA47 SA48 SA49
SG12
01100 SA50 SA51 SA52 SA53
SG13
01101 SA54 SA55 SA56 SA57
SG14
01110 SA58 SA59 SA60 SA61
SG15
01111 SA62 SA63
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Sector Group
A21-A17
Sector
SA64 SA65
A21
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A20
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (hexadecimal)
200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF 268000-26FFFF 270000-277FFF 278000-27FFFF 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF 2F8000-2FFFFF
SG16
10000 SA66 SA67 SA68 SA69
SG17
10001 SA70 SA71 SA72 SA73
SG18
10010 SA74 SA75 SA76 SA77
SG19
10011 SA78 SA79 SA80 SA81
SG20
10100 SA82 SA83 SA84 SA85
SG21
10101 SA86 SA87 SA88 SA89
SG22
10110 SA90 SA91 SA92 SA93
SG23
10111 SA94 SA95
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Sector Group
A21-A17
Sector
SA96 SA97
A21
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A20
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (hexadecimal)
300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF
SG24
11000 SA98 SA99 SA100 SA101
SG25
11001 SA102 SA103 SA104 SA105
SG26
11010 SA106 SA107 SA108 SA109
SG27
11011 SA110 SA111 SA112 SA113
SG28
11100 SA114 SA115 SA116 SA117
SG29
11101 SA118 SA119 SA120 SA121
SG30
11110 SA122 SA123 SA124 SA125
SG31
11111 SA126 SA127
Note: The sizes of all sectors are 32K-word.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U USER MODE DEFINITIONS
TABLE 3. BUS OPERATIONS
Operation Read Write Accelerated Program CMOS Standby TTL Standby Output Disable Hardware Reset Sector Group Protect
CE# L L L VBcc 0.3V
B
OE# L H H X X H X
WE# H L L X X H X
RESET# H H H VBcc 0.3V
B
WP# X (Note 1) (Note 1) X X X X
ACC X X VBHH
B
A21-A0 ABIN
B
DQ15-DQ0 DBOUT
B
ABIN
B
(Note 3)B
B
ABIN X X X X
(Note 3)B High-Z High-Z High-Z High-Z
H H X X
H L X
H H L
L
H
L
VBID
B
H
X
Sector Group Unprotect Temporary Sector Group Unprotect
B
L
H
L
VBID
B
H
X
SA, A6=L, A1=H, A0=L SA, A6=H, A1=H, A0=L ABIN
B
(Note 3)
(Note 3)
X
X
X
VBID
B
H
X
(Note 3)
L=logic low= VBIL, H=Logic High= VBIH, VBID = VHH = 11 0.5V = 10.5 11.5V, X=Don't Care (either L or H, but not floating!), SA=Sector Addresses (A21-A15), DBIN=Data In, DBOUT=Data Out, ABIN=Address In
B B B B B
Notes: 1. If the system asserts VBIL on the WP# pin, the device disables program and erase functions in the first or last sector independent of whether those sectors were protected or unprotected; if the system asserts VBIH on the WP# pin, the device reverts to whether the first or last sector was previously protected or unprotected. If ACC = VBHH, all sectors will be unprotected.
B
2. Please refer to "Sector Group Protection & Unprotection", Flowchart 6a and Flowchart 6b. 3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm.
Read Mode
The device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm After the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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data with the same exception. See "Sector Erase Suspend/Resume Commands" for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the "Reset Command" for additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VBIH), the output from the device is disabled. The output pins are placed in a high impedance state.
B
Standby Mode
The device has a CMOS-compatible standby mode, which reduces the current to < 1A (typical). It is placed in CMOS-compatible standby when the CE# pin is at VBCC 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum VBCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at VBIH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.
B B B B
Automatic Sleep Mode
The device has an automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.
Writing Command Sequences
To write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to VBIL, and OE# to VBIH.
B
The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the "Command Definitions" for all the available commands.
Autoselect Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VBID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The "Command Definitions" table shows the remaining address bits that are don't-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0.
B
To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VBID. See "Command Definitions" for details on using the autoselect mode. Note that a Reset command is required to return to read mode when the device is in the autoselect mode.
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2005/06/27
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TABLE 4. Autoselect Codes (Using High Voltage, VBID)
B
Description
CE#
OE#
WE#
A21 to A15 X
A14 to A10 X
A9P
2
P
A8 HP
1
P
A7
A6
A5 to A2 X
A1
A0
DQ15 to DQ0 XX1Ch
Manufacturer ID: Eon Autoselect Device ID Sector Protection Verification
L
L
H
VBID
B
X L
L
L
L XX7Fh
L
L
H
X
X
VBID
B
X
X
L
X
L
H
22D7h XX01h
L
L
H
SA
X
VBID
B
X
X
L
X
H
L
(Protected)
XX00h
(Unprotected)
L=logic low= VBIL, H=Logic High= VBIH, VBID =11 0.5V, X=Don't Care (either L or H, but not floating!), SA=Sector Addresses
B B B
Note: 1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. 2. A9 = VBID is for HV A9 Autoselect mode only. A9 must be Vcc (CMOS logic level) for Command Autoselect Mode.
B
ACC: Accelerated Program Operation
The device offers accelerated program operation which enables the programming in higher speed. When ACC is raised to VHH, the memory automatically enters the Unlock Bypass mode (please refer to "Command Definitions"), temporarily unprotects every protected sector groups, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When ACC returns to VIH or VIL, normal operation resumes. The transitions from VIH or VIL to VHH and from VHH to VIH or VIL must be slower than tVHH, see Figure 5. Note that the ACC pin must not be left floating or unconnected. In addition, ACC pin must not be at VHH for operations other than accelerated program. It could cause the device to be damaged. Never raise this pin to VHH from any mode except Read mode; otherwise the memory may be left in an indeterminate state. A 0.1F capacitor should be connected between the ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program.
RESET#: Hardware Reset
When RESET# is driven low for tBRP, all output pins are tristates. All commands written in the internal state machine are reset to reading array data.
B
Please refer to timing diagram for RESET# pin in "AC Characteristics".
Sector Group Protection & Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group. The hardware chip unprotection feature re-enables both program and erase operations in previously
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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protected sector group. A sector group consists of four adjacent sectors that would be protected at the same time. Please see Table 2 which show the organization of sector groups.
There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 6a and 6b for the algorithm and Figure 11 for the timings. When doing Sector Group Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle. The second method is for programming equipment. This method requires VID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document, the Datasheet Supplement of EN29LV641H/L / EN29LV640U, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.
U
WP#: Write Protect
The Write Protect function provides a hardware method to protect the first or last sector against erase and program without using VID. When WP# is Low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in "Sector Group Protection & Unprotection", Program and Erase operations in these sectors are ignored. When WP# is High, the device reverts to the previous protection status of the first or last sector. Program and Erase operations can now modify the data in those sectors unless the sector is protected using Sector Group Protection. Note that the WP# pin must not be left floating or unconnected.
Temporary Sector Group Unprotect
Start
This feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Group Unprotect mode is activated by setting the RESET# pin to VBIDB. During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. Once VBIDB is removed from the RESET# pin, all the previously protected sector groups are protected again. See accompanying flowchart and timing diagrams in Figure 10 for more details.
Notes: 1. All protected sector groups are unprotected. (If WP#=VBIL, the first or last sector will remain protected.) 2. Previously protected sector groups are protected again.
B
Reset#=VBID (note 1)
B B B
Perform Erase or Program Operations RESET#=VBIH
B
Temporary Sector Group Unprotect Completed (note 2)
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC IDindependent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8.The upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5-8. The system must write the reset command to return the device to the autoselect mode.
Table 5. CFI Query Identification String
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 6. System Interface String
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0003h 0000h 000Ah 0000h 0005h 0000h 0002h 0000h Description Vcc Min (write/erase) DQ7-DQ4: volt, DQ3 -DQ0: 100 millivolt Vcc Max (write/erase) DQ7-DQ4: volt, DQ3 -DQ0: 100 millivolt Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) Typical timeout per single byte/word write 2PN S Typical timeout for Min, size buffer write 2PN S (00h = not supported) Typical timeout per individual block erase 2PN ms Typical timeout for full chip erase 2PN ms (00h = not supported) Max. timeout for byte/word write 2PN times typical Max. timeout for buffer write 2PN times typical Max. timeout per individual block erase 2PN times typical Max timeout for full chip erase 2PN times typical (00h = not supported)
P P P P P P P P
Table 7. Device Geometry Definition
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0017h 0001h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Description Device Size = 2PN bytes
P
Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2PN (00h = not supported) Number of Erase Block Regions within device
P
Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 8. Primary Vendor-specific Extended Query
Addresses 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh Data 0050h 0052h 0049h 0031h 0033h 0004h 0002h 0004h 0001h 0004h 0000h 0000h 0000h 00A5h 00B5h 00XXh Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Minimum ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV Maximum ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 00h = Uniform Sector Devices
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV641H/L EN29LV640U Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.
Low VBCC Write Inhibit
B
When VCC is less than VBLKO, the device does not accept any write cycles. This protects data during VCC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VBLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VBLKO.
B B B
Write Pulse "Glitch" protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VBIL, CE# = VBIH, or WE# = VBIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.
B B B
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VBIL, WE#= VBIL and OE# = VBIH, the device will not accept commands on the rising edge of WE#.
B B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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COMMAND DEFINITIONS
The operations of the device are selected by one or more commands written into the command register. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.
Table 9. EN29LV641H/L / EN29LV640U Command Definitions
Bus Cycles (Note 1-2) Command Sequence Read (Note 3) Reset Autoselect Manufacturer ID Device ID Sector Protect Verify (Note 4)
Cycles
1P Cycle
P
st
2P
nd
P
Cycle
3P Cycle
P
rd
4P Cycle
P
th
5P Cycle
P
th
6P Cycle
P
th
1 1 4 4 4 4 3 2 2 6 6 1 1 1
RA xxx 555 555 555 555 555 XXX XXX 555 555 BA BA 55
RD F0 AA AA AA AA AA A0 90 AA AA B0 30 98 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 555 555 555 555 555 90 90 90 A0 20 000 100 X01 (SA) X02 PA 7F 1C 22D7 XX00 XX01 PD
Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume CFI Query
Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don't-Care PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the Sector to be erased or verified (in Autoselect mode). Address bits A21-A15 uniquely select any Sector.
Notes: 1. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 2. Unless otherwise noted, address bits A21-A15 are don't cares. 3. No unlock or command cycles required when device is in read mode. 4. The data is 00h for an unprotected sector group and 01h for a protected sector group.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following an Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can read array data using the standard read timings from sectors other than the one which is being erase-suspended. If the system reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high during an active program or erase operation or while in the autoselect mode. See next section for details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't-care for this command. The reset command may be written between the cycle sequences in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the cycle sequences in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Sector Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the cycle sequences in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies in Sector Erase Suspend mode).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices ID codes, and determine whether or not a sector group is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VBID on address bit A9 and is intended for commercial programmers.
B
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data.
Word Programming Command
Programming is performed by using a four-bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Any commands written to the device during the program operation are ignored. Programming status can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a "0" to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". When programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can return the device to Read mode. Programming is allowed in any sequence across sector boundaries.
Unlock Bypass
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two-cycle Unlock Bypass Program command can be used instead of the normal four-cycle Program Command to program the device. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset command can be accepted. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled The device provides accelerated program operations through the ACC pin. When ACC is asserted to VBHH, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass Program command sequence.
B
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. If there are several sectors to be erased, Sector Erase Command sequences must be issued for each sector. That is, only a sector address can be specified for each Sector Erase command. Users must issue another Sector Erase command for the next sector to be erased after the previous one is completed. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Sector Erase Suspend / Resume Command
The Sector Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Sector Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don't-cares when writing the Sector Erase Suspend command. When the Sector Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Please note that Autoselect command sequence can not be accepted during Sector Erase Suspend. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The Autoselect command is not supported during Sector Erase Suspend Mode. The system must write the Sector Erase Resume command (address bits are don't-care) to exit the sector erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Sector Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7: DATA# Polling
The device provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the Programming, Sector Erase, Chip Erase, and Sector Erase Suspend. (See Table 10) When the embedded programming is in progress, an attempt to read the device will produce the complement of the data written to DQ7. Upon the completion of the programming operation, an attempt to read the device will produce the true data written to DQ7. DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence for program. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising edge of the last WE# or CE# pulse in the six-cycle sequence. DATA# Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected sector.
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Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on the time the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 should be read on the subsequent read attempts. The flowchart for DATA# Polling (DQ7) is shown on Flowchart 4. The DATA# Polling (DQ7) timing diagram is shown in Figure 6.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. In the output-low period, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The device provides a "Toggle Bit" on DQ6 to indicate the status of the embedded programming and erase operations. (See Table 10) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# or CE#) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector erase or chip erase. In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 s. The chip will then return to the read mode without changing data in all protected sectors. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 5. The Toggle Bit timing diagram is shown in Figure 7.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a "1" on DQ5. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be checked to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) When sector erase starts, DQ3 switches from "0" to "1". This device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a "1" after the first 30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The "Toggle Bit" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to the following table to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, after the initial two read cycles, the system determines that the toggle bit is still toggling. And the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Write Operation Status
Operation Standard Mode Sector Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend Program DQ7 DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No Toggle Data Toggle DQ5 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Table 10. Status Register Bits
DQ Name Logic Level `1' 7 Definition Erase Complete or erased sector in Sector Erase Suspend Erase On-Going Program Complete or data of non-erased sector during Sector Erase Suspend Program On-Going Erase or Program On-going Read during Sector Erase Suspend Erase Complete Program or Erase Error Program or Erase On-going Erase operation start Erase timeout period on-going Chip Erase, Sector Erase or Read within EraseSuspended sector. (When DQ5=1, Erase Error due to currently addressed Sector or Program on Erase-Suspended sector Read on addresses of non Erase-Suspend sectors
DATA#
POLLING
`0' DQ7 DQ7# `-1-0-1-0-1-0-1-'
6
TOGGLE BIT
DQ6 `-1-1-1-1-1-1-1-` `1' `0'
5
ERROR BIT SECTOR ERASE TIME BIT
3
`1' `0'
2
TOGGLE BIT
`-1-0-1-0-1-0-1-'
DQ2
Notes:
DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5: Error Bit: set to "1" if failure in programming or erase DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 1. Embedded Chip Erase
START
Write Data AAh to Address 555h
Write Data 55h to Address 2AAh
Write Data 80h to Address 555h
Write Data AAh to Address 555h
Write Data 55h to Address 2AAh
Write Data 10h to Address 555h
Data Poll from System Embedded Chip Erase in progress
No
DATA = FFh?
Yes Erasure Completed
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 2. Embedded Sector Erase
START
Write Data AAh to Address 555h
Write Data 55h to Address 2AAh
Write Data 80h to Address 555h
Write Data AAh to Address 555h
Write Data 55h to Address 2AAh
Write Data 30h to Sector Address
Data Poll from System Embedded Sector Erase in progress
No
DATA = FFh? Yes
No Last Sector to Erase?
Yes Erasure Completed
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 3. Embedded Program
START
Write Data AAh to Address 555h
Write Data 55h to Address 2AAh
Write Data A0h to Address 555h
Write Programmed Data to Destination Address
Data Poll from System Embedded Program in progress
No
Verify OK?
Yes No
Increment Address
Last Address?
Yes Program Completed
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 4. DATA# Polling Algorithm
Start
Read DQ7-DQ0 Adr = VA
DQ7 = Data? No No
Yes
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be re-checked even if DQ5 = "1" in case the first set of reads was done at the exact instant when the status data was in transition.
DQ5 = 1? Yes Read DQ7-DQ0 Adr = VA
Yes DQ7 = Data? No Fail Pass
Flowchart 5. Toggle Bit Algorithm
Start
Read DQ7-DQ0 twice No DQ6 = Toggle? Yes No DQ5 = 1? Yes
Notes: 1. The system should be re-checked the toggle bit even if DQ5 = "1" in case the first set of reads was done at the exact instant when the status data was in transition.
Read DQ7-DQ0 No DQ6 = Toggle? Yes Fail Pass
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 6a. In-System Sector Group Protect Flowchart
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Group Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector group address
To Protect: Write 60h to sector group addr with A6 = 0, A1 = 1, A0 = 0
Wait 150 s To Verify: Write 40h to sector group address with A6 = 0, A1 = 1, A0 = 0 Increment PLSCNT Wait 0.4 s Reset PLSCNT = 1
No No
Read from sector address with A6 = 0, A1 = 1, A0
PLSCNT = 25?
Data = 01h?
Yes
Yes
Device failed Protect another sector? No Remove VID from RESET# Write reset command Yes
Sector Group Protect Algorithm
Sector Group Protect complete
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 6b. In-System Sector Group Unprotect Flowchart
START
PLSCNT = 1 Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see Diagram 6a.) RESET# = VID Wait 1 S
No First Write Cycle = 60h? Temporary Sector Group Unprotect Mode
Yes No All sectors protected?
Yes Set up first sector group address Unprotect: Write 60H to sector address with A6 = 1, A1 = 1, A0 = 0
Wait 15 ms
Increment PLSCNT
Verify Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 =0
Wait 0.4 S
No
Read from sector group address with A6 = 1, A1 = 1, A0 = 0
PLSCCNT = 1000? Yes Device failed
No
Data = 00h? Yes
Set up next sector group address
Last sector group verified? Yes Remove VID from RESET#
No
Write reset command
Sector Group Unprotect complete
Sector Group Unprotect Algorithm
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV641H/L EN29LV640U
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit CurrentP1
P
Value -65 to +125 -65 to +125 -55 to +125 200 -0.5 to 4.0 -0.5 to 5.5 -0.5 to +11.5 0.5 to VCC + 0.5
P
Unit C C C mA V V V V
VCC Voltage with Respect to Ground VIO A9, OE#, ACC and RESET# 2
P P
All other pins 3
P
Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is -0.5V. During voltage transitions, A9, OE#, RESET# and WP#/ACC pins may undershoot VBss to -1.0V for periods of up to 50ns and to -2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VBss to -1.0V for periods of up to 50ns and to -2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is VBcc + 0.5 V. During voltage transitions, outputs may overshoot to VBcc + 1.5 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B B B B
RECOMMENDED OPERATING RANGESP1
P
Parameter Ambient Operating Temperature Commercial Devices Industrial Devices Operating Supply Voltage VCC
Value 0 to 70 -40 to 85 Full Voltage Range:2.7 to 3.6V Regulated Voltage Range:3.0 to 3.6V
Unit C
V
1.Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Maximum Negative Overshoot
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Maximum Positive Overshoot 30
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
Waveform Waveform
DC Characteristics Table 11. DC Characteristics
Symbol IBLI
B
Parameter Input Leakage Current
Test Conditions 0V VBIN VCC
B
Min
Typ
Max 5 35 5
Unit A A A mA mA
IBLIT
B
A9, ACC Input Load Current Output Leakage Current
B
A9 = 11.5V 0V VBOUT VCC
B
IBLO
B
IBCC1 IBCC2
B
Supply Current (read)
CE# = VBIL ; OE# =
B
VBIH ; f = 5MHZ
B
9 20
16 30
Supply Current (Program or Erase)
CE# = VBIL, OE# =
B
IBCC3
Supply Current (Standby - CMOS)
VBIH , WE# = VBIL CE# = BYTE# = RESET# = VCC 0.3V (Note 1)
B B
1
5.0
A
IBCC4
B
Reset Current
RESET# = VSS 0.3V VBIH = VCC 0.3V
B
1
5.0
mA
IBCC5
B
Automatic Sleep Mode Input Low Voltage
VBIL = VSS 0.3V,
B
1 -0.5 0.7 x VCC 10.5 10.5
5.0 0.8 Vcc 0.3 11.5 11.5 0.45
uA V V V V V V V
WP# = VBIH VBIL
B
VBIH
B
Input High Voltage
B
VBHH VBID
B
VBOL
B
Voltage for ACC Program Acceleration Voltage for Autoselect or Temporary Sector Unprotect Output Low Voltage Output High Voltage TTL
IBOL = 4.0 mA
B
IBOH = -2.0 mA
B
VBOH
B
Output High Voltage CMOS VBLKO
B
IBOH = -100 A,
B
0.85 x VCC VCC 0.4V 2.3 2.5
Supply voltage (Erase and Program lock-out)
V
Notes:
1. Maximum IBCC specifications are tested with VCC = VCC max.
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
Test Conditions
3.3 V
2.7 k
Device under Test
CL
6.2 k
Note: Diodes are IN3064 or equivalent
Test Specifications
Test Conditions Output Load Output Load Capacitance, CBL
B
70R
90
Unit
1 TTL Gate 30 5 0.0-3.0 1.5 0.5VIO 30 5 0.0-3.0 1.5 0.5VIO pF ns V V V
Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels .
Key to Switching Waveforms
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
32
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
AC CHARACTERISTICS Table 13. Read-only Operations Characteristics
Parameter Symbols JEDEC Standard Description Read Cycle Time
B
Test Setup Min CE# = VBIL OE#B = VIL
B B B B B
Speed Options 70R 70 70 70 30 20 20 0 0 10 90 90 90 90 35 20 20 0 0 10 Unit ns ns ns ns ns ns ns ns ns
tBAVAV
B
tBRC
B B
tBAVQV tBELQV
B
tBACC tBCE
B
Address to Output Delay Chip Enable To Output Delay
Max Max Max Max Max Min Min Min
OE#B = VBIL
B B
tBGLQV
B
tBOE
B
Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE# or OE#, whichever occurs first
B
tBEHQZ
B
tBDF
B B
tBGHQZ tBAXQX
B
tBDF
B
tBOH
tBOEH
B
Output Enable Hold Time
Read Toggle and Data# Polling
Figure 2. AC Waveforms for READ Operations
tRC
Addresses
Addresses Stable
tACC
CE#
tDF tOE tOEH
OE#
WE#
tCE
Output Valid
tOH
HIGH Z
Outputs
Reset#
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
33
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
AC CHARACTERISTICS Hardware Reset (RESET#) Table 12. Hardware Reset Operations Characteristics
Parameter tBREADY
B
Description RESET# Pin Low to Read or Write Embedded Algorithms RESET# Pin Low to Read or Write Non Embedded Algorithms RESET# Pulse Width RESET# High Time Before Read Max Max Min Min
All Speed options 20 500 500 50
Uni t s nS nS nS
tBREADY
B
tBRP
B
tBRH
B
Figure 1. AC Waveforms for RESET# Reset# Timings
CE# OE#
tRH
RESET#
tRP
tREADY
Reset Timings NOT During Automatic Algorithms
tREADY
CE# OE#
RESET#
tRP
tRH
Reset Timings during Automatic Algorithms
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
34
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
AC CHARACTERISTICS Table 14. Write (Erase/Program) Operations
Parameter Symbols JEDEC Standard Description Write Cycle Time
B
Speed Options 70R Min Min Min Min Min Min Min Min Min Min Min 70 0 40 40 0 20 0 0 0 30 25 90 90 0 40 40 0 20 0 0 0 30 25 Unit ns ns ns ns ns ns ns ns ns ns ns
tBAVAV
B
tBWC
B
tBAVWL tBWLAX
B
tBAS
B
Address Setup Time
B
tBAH
B
Address Hold Time Data Setup Time
B
tBDVWH tBWHDX
B
tBDS
B
tBDH tBOEH
B
Data Hold Time Output Enable Hold Time during Toggle and DATA# Polling Read Recovery Time before Write (OE# High to WE# Low)
B
tBGHWL
B
tBGHWL tBCS
B
tBELWL
B
CE# Setup Time
B
tBWHEH
B
tBCH
B
CE# Hold Time
B
tBWLWH tBWHDL
B
tBWP
Write Pulse Width
B
tBWPH
Write Pulse Width High
tBWHWH1
tBWHWH1
B
Programming Operation
Typ
8
8
s
tBWHWH1
B
tBWHWH1
B
Accelerated Programming Operation
Typ
5
5
s
tBWHWH2
B
tBWHWH2
B
Sector Erase Operation
Typ
0.5
0.5
s
tBWHWH3
B
tBWHWH3
B
Chip Erase Operation
Typ
64
64
s
tBVHH
B
VHH Rise and Fall Time VCC Setup Time
Min Min
250 50
250 50
ns s
tBVCS
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
35
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
AC CHARACTERISTICS Table 15. Write (Erase/Program) Operations
Alternate CE# Controlled Writes Parameter Symbols JEDEC Standard Description Write Cycle Time
B
Speed Options 70R Min Min Min Min Min Min Min Min Min Min Typ 70 0 40 40 0 0 0 0 35 20 8 90 90 0 40 40 0 0 0 0 45 20 8 Unit ns ns ns ns ns ns ns ns ns ns s
tBAVAV
B
tBWC tBAS
B
tBAVEL
B
Address Setup Time
B
tBELAX
B
tBAH
B
Address Hold Time Data Setup Time
B
tBDVEH tBEHDX
B
tBDS
B
tBDH tBGHEL
B
Data Hold Time Read Recovery Time before Write (OE# High to CE# Low) WE# Setup Time
B B
tBGHEL
B
tBWLEL
B
tBWS
B
tBEHWH tBELEH
B
tBWH tBCP
B
WE# Hold Time CE# Pulse Width
B
tBEHEL
B
tBCPH
B
CE# Pulse Width High Programming Operation
B
tBWHWH1
tBWHWH1
tBWHWH1
B
tBWHWH1
B
Accelerated Programming Operation
Typ
5
5
s
tBWHWH2
B
tBWHWH2
B
Sector Erase Operation
Typ
0.5
0.5
s
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
36
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
AC CHARACTERISTICS Figure 3. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)
tWC Addresses 0x2AA
tAS SA
tAH VA
0x555 for chip erase
VA
CE# TGHWL OE# tWP WE# tCS tWPH tCH
tWHWH2 or tWHWH3 Data 0x55 tDS 0x30 tBUSY Status DOUT
tDH
tRB
RY/BY#
VCC
tVCS
Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, DBout =true data at read address. 2. VBcc is shown only to illustrate tBvcs measurement references. It cannot occur as shown during a valid command sequence.
B B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
37
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
Figure 4. Program Operation Timings
Program Command Sequence (last 2 cycles) Program Command Sequence (last 2 cycles)
tWC Addresses 0x555
tAS PA
tAH PA PA
CE# tGHWL OE# tWP WE# tCS Data tDS tDH RY/BY# tVCS tBUSY
OxA0
tCH
tWPH tWHWH1 PD Status DOUT tRB
VCC
Notes: 1. PA=Program Address, PD=Program Data, DBOUT is the true data at the program address. 2. VBCC shown in order to illustrate tBVCS measurement references. It cannot occur as shown during a valid command sequence.
B B B
Figure 5. Accelerated Program Timing Diagram
VBHH
B
ACC
0 or 3 V
0 or 3 V tBVHH
B
tBVHH
B
CE#
WE# tBRSP
B
AC CHARACTERISTICS
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
38
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm Operations
tRC Addresses tCH CE#
VA VA VA
tACC tCE
tOE OE# tOEH
tDF
WE#
tOH
DQ[7]
Complement
Complement
True
Valid Data
DQ[6:0] TBUSY RY/BY#
Notes:
Status Data
Status Data
True
Valid Data
1. VA = Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC Addresses tCH CE# VA tACC tCE VA VA VA
tOE OE# tOEH
tDF
WE#
tOH
DQ6, DQ2 tBUSY RY/BY#
Valid Status (first read)
Valid Status (second d)
Valid Status (stops toggling)
Valid Data
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
39
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
Figure 8. Alternate CE# Controlled Write Operation Timings
0x555 for Program 0x2AA for Erase PA for Program SA for Sector Erase 0x555 for Chip Erase
Addresses tWC WE# tGHEL OE# tWS CE# tDS Data
0xA0 for Program
PD for Program 0x30 for Sector Erase 0x10 for Chip Erase
VA
tAS
tAH
tWH
tCP
tCPH
tCWHWH1 / tCWHWH2 / tCWHWH3
tDH
tBUSY Status DOUT
RY/BY# tRH Reset#
Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status DBout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle RESETt# shown to illustrate tBRH measurement references. It cannot occur as shown during a valid command sequence.
B B
Figure 9. DQ2 vs. DQ6
Enter Embedded Erase Erase Suspend Enter Erase Suspend Program Enter Suspend Read Enter Suspend Program Erase Resume
WE#
Erase
Erase Suspend Read
Erase
Erase Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
40
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
AC CHARACTERISTICS Temporary Sector Group Unprotect
Parameter Std tBVIDR
B B
Description VBID Rise and Fall Time Min Min Min
Speed Option 70R 90 500 500 4
Unit Ns Ns
s
tBVIHH
B
tBRSP
B
VBHH Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect
B
Figure 10. Temporary Sector Group Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V tVIDR tVIDR
CE#
WE# tRSP
AC CHARACTERISTICS Figure 11. Sector Group Protect and Unprotect Timing Diagram
VID RESET#
Vcc 0V 0V
tVIDR
tVIDR
SA, A6,A1,A0 Data 60h
Valid 60h
Valid 40h Verify >0.4S
Valid Status
Sector Protect/Unprotect CE# WE# >1S OE#
Protect: 150 uS Unprotect: 15 mS
Notes: Use standard microprocessor timings for this device for read and write cycles. For Sector Group Protect, use A6=0, A1=1, A0=0. For Sector Group Unprotect, use A6=1, A1=1, A0=0.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
41
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
ERASE AND PROGRAM PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Word Programming Time Accelerated Word Program Time Chip Programming Time Erase/Program Endurance Typ 0.5 64 8 5 20 100K 300 120 60 Limits Max 10 Unit Sec Sec S S Sec Cycles Minimum 100K cycles Excludes system level overhead Comments Excludes 00h programming prior to erasure
Note: Typical Conditions are room temperature, 3V and checkboard pattern programmed.
LATCH UP CHARACTERISTICS
Parameter Description Input voltage with respect to VBss on all pins except I/O pins (including A9, Reset and OE#)
B
Min -1.0 V -1.0 V -100 mA
Max 12.0 V VCC + 1.0 V 100 mA
Input voltage with respect to VBss on all I/O Pins
B
VCC Current
Note: These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
48-PIN TSOP PACKAGE CAPACITANCE
Parameter Symbol CBIN
B
Parameter Description Input Capacitance
Test Setup VBIN = 0
B
Typ 6 8.5 7.5
Max 7.5 12 9
Unit pF pF pF
CBOUT
B
Output Capacitance Control Pin Capacitance
VBOUT = 0
B
CBIN2
B
VBIN = 0
B
Note: Test conditions are Temperature = 25C and f = 1.0 MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
42
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
FIGURE 12. TSOP 12mm x 20mm
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
43
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
44
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
FIGURE 13. 63-TFBGA 11mm x 12mm package outline
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
45
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
EN29LV641H/L EN29LV640U
Revisions History
Revision No A Description Initial Release 1. VIO input should be tied to VCC only not supporting to 1.8V output 2. revise the package code for 63 balls TFBGA from "B" to "W" at
page 5
Date 2005/02/21
B
3. a typo at tOE specification at page 2 and page 33, it shall be 30 ns
and 35ns for 70R ns and 90ns product respectively.
2005/06/27
4. Icc3 stand by current only reserves the CMOS condition
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
46
(c)2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27

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